Advances in surface mount technology and printed circuit (PC) board manufacture have resulted in more complex and smaller PC boards that have higher integrated circuit (IC) density. Surface mount devices (SMDs) or very large-scale integrated (VLSI) circuits often have minimal spacing between pins. SMDs may be now mounted to both sides of the PC board.
“Contact” test methods for such devices (in which the test fixture directly contacts the pins or other electrical contacts on the board), have become correspondingly more complex and costly. In order to test certain devices with higher pin pitches, some test fixtures are configured with smaller probe tips or alternate electrical contact apparatus. Similarly, testing devices having ICs mounted on both sides of the PC board has sometimes required substantial modification of pre-existing text fixtures.
In 1990, the Institute of Electrical and Electronic Engineers (IEEE) adopted a standard for a non-contact method of testing PC boards. According to the 1149.1 standard, also known as the IEEE Standard Test Access Port and Boundary Scan Architecture, logic can be incorporated into an IC that may allow for test methods that may include in-circuit testing of an IC itself, interconnection testing of interconnections between ICs in an assembled PC board, and operational testing for observing and modifying of circuit activity during normal operation. The test logic may allow software to control and observe boundary scan cells electronically during test or normal operation. A boundary scan cell may be located adjacent to each IC pin so that signals at the IC boundaries can be controlled and observed. Each boundary scan cell may include a shift register stage. The boundary scan cells may allow test data to be electronically placed on an output pin or to be observed electronically on an input pin for an IC without the need for a physical probe. The boundary scan cells for the pins of an IC may be interconnected to form a shift register chain. The chain may include serial input and output connections and clock and control signals. The test data may be shifted serially into and out of boundary scan registers that can be connected on a bus within the IC. The boundary scan bus and other building blocks may be accessed through a Test Access Port (TAP).
In many conventional implementations, the TAP controls an interface between the boundary scan registers on the IC and the boundary scan bus. The TAP can be implemented as a state machine controlling the operations associated with the boundary scan cells. The TAP controller interface can be based on four ports. The Test Clock (TCK), Test Mode Select (TMS), Test Data In (TDI), and Test Data Out (TDO) ports may be used to control the basic operation of the TAP. The TCK and TMS ports may direct signals between TAP controller states. The TDI and TDO ports may receive the data input and output values serially from the boundary scan registers. An optional fifth port, Test Reset (TRST), may be implemented as an asynchronous reset signal to the TAP controller.
A serial protocol, such as Joint Test Action Group (JTAG) can be used to communicate with the TAP controller in certain implementations. A JTAG device, e.g., an external test device, can use the JTAG protocol to implement a full duplex serial synchronous protocol for communication with the TAP controller. A JTAG master, that forms part of the JTAG device, and TAP controller may include logic for accessing internal memory devices of a microcontroller, for example.